1. Field of the Invention
The present invention relates to the field of liquid crystal displaying technology, and in particular to a gate-drive-on-array (GOA) circuit for use with oxide semiconductor thin-film transistors.
2. The Related Arts
GOA (Gate Drive on Array) refers to forming a gate column-scanning drive signal circuit on a thin-film transistor (TFT) array substrate with an array process of a TFT liquid crystal display in order to achieve a column-by-column scanning gate driving method.
For conventional amorphous silicon semiconductor devices, since the threshold voltage Vth of the electrical characteristics of an amorphous silicon TFT is, in general, greater than 0V and the voltage swing with respect to current in a sub-threshold area is relatively large. In a circuit with such a design, even though some transistors are operating in a condition that the voltage Vgs between the gate and the source of the transistor is around 0V, the leakage current is relatively small. However, for oxide semiconductor thin-film transistors that are currently under development, due to the material property of such semiconductor materials being different from those of amorphous silicon, the threshold voltage Vth of such thin-film transistors may sometime becomes less than 0V and the voltage swing with respect to current in the sub-threshold area is relatively small. This leads to a relatively great leakage current for some important transistors included in a circuit when they are operating around Vgs=0V. Thus, a particular design solution must be adopted for a gate-drive-on-array circuit of oxide semiconductor thin-film transistors, in order to prevent some important thin-film transistors from operating around Vgs being equal to 0V.
As shown in FIG. 1, which is a conventional gate-drive-on-array circuit for use with amorphous silicon thin-film transistors, the primary architecture of the circuit comprises: a up-pull control portion 100, a up-pull portion 200, a down-transfer portion 300, a first down-pull portion 400, a bootstrap capacitor 500, and a down-pull holding portion 600.
Control signal sources of the gate-drive-on-array circuit for use with amorphous silicon thin-film transistors generally include a high-frequency clock signal CK(n), a constant-voltage low potential source VSS, and low-frequency clock signals LC1 and LC2, wherein LC1 and LC2 are low-frequency signal sources having opposite phases. In setting a general CK(n), the low potentials of LC1 and LC2 would be less than VSS, but the key nodes Q(N) and G(N) of the circuit will both be pulled down to VSS during a non-operating period. As such, for a twenty-first transistor T21 of the up-pull portion 200 and a twenty-second transistor T22 of the down-transfer portion 300, the essential operation voltage VgsP≈0V, and Q(N) is susceptible to fluctuations between highs and lows. In other words, the situation that Vgs>0V might exist. Then, when the circuit is applied directly to the design of a drive circuit for oxide semiconductor thin-film transistors, there will be a relatively large leakage current, making it not possible to ensure the output terminal G(N) maintains at a low potential during a non-operating period. This would lead to poor output of the output terminal G(N) and poor performance of the GOA circuit.
Similarly, the same issues are equally applicable to a thirty-first transistor T31 and the forty-first transistor T41 of the first down-pull portion 400. During an operating period when Q(N) and G(N) are of high potentials, the leakage currents of T31 and T41 would cause distortion of the output waveform of Q(N) and G(N) thereby leading the poor functionality of the GOA circuit in a severe condition (such as operation in high temperatures).
For the down-pull holding circuit portion 600, since the circuit design uses the low potential of LC1 or LC2 to control down pulling of P(N) or K(N) in an operating period, this ensures the low potentials of P(N) and K(N) less than VSS during an operating period and ensuring Vgs<0V for the thirty-second, thirty-third, forty-second, and forty-third transistors T32, T33, T42, T43 in a well closed condition thereby reducing the influence of the down-pull holding circuit portion 600 on the output waveforms of Q(N) and G(N). However, in the design solution that is currently adopted, a bridge TFT T55 of the down-pull holding circuit portion shows Vgs>0V in a non-operating period. This makes the high potential of P(N) or K(N) not raised very high during a non-operating period, thereby affecting the down-pulling effect of T32, T33, T42, and T43 on Q(N) and G(N). This issue, although being improvable through adjusting device size in making a design, causes another problem of increasing leakage current due to the increase of the size.